Along with increase of requirements of users on network bandwidths, requirements on equipment interface rates also increase, from 10 Gb/s to 40 Gb/s and then to 100 Gb/s, 400 Gb/s and even 1 Tb/s. For a service at a level of higher than 100 Gb/s, transmission of the whole service cannot be finished by only one physical channel, and at present, such a problem is solved mainly by adopting a multi-channel method.
A principle for multi-channel transmission is to evenly distribute the whole high-bandwidth data to n (n>1) independent physical channels at a data sender and then restore the data of the n independent physical channels into the complete data sent by the data sender through a certain restoration mechanism at a data receiver. Multi-channel data transmission solves the problem of limitation to a single-port rate of a conventional chip and makes higher-bandwidth data transmission possible.
100 Gb/s, 40 Gb/s and 100 Gb/s multi-channel data alignment and restoration standards have been sequentially proposed. However, a conventional higher-than-40 Gb/s multi-channel data alignment and restoration standard is only applied to a physical channel with an interface rate of lower than 12 G/bs, and 400 Gb/s multi-channel data may adopt a single-path rate of 28 Gb/s, which has yet not been implemented at present. Further, the conventional higher-than-40 Gb/s multi-channel data alignment and restoration standard replaces data with a bit data stream at the sender and adopts the replacing bit data stream for data alignment and restoration at the receiver, the implementation of such a method is a tedious process, and when there is great data offset between channels, finishing searching all of the data is a great challenge for controlling a chip resource time sequence, restoration of the data is relatively slow, and chip implementation cost is excessively high.